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fedl610q174-01 issue date: oct 25, 2013 ML610Q174 the low power micro controller corresponding to 5v for household appliances i 1/26 general description this lsi is a high-performance 8-bit cmos microcontrolle r into which rich peripheral circuits, such as 10-bit a/d converter, timer, pwm, synchronous serial port, uart, i2c bus interface (master), battery level detect circuit, lcd driver, are incorporat ed around 8-bit cpu nx-u8/100. the cpu nx-u8/100 is capable of efficient instruction execution in 1-instruction 1-clock mode by 3-stage pipe line architecture parallel procesing. the on-chip debug function that is installed enables program debugging and programming. features ? cpu ? 8-bit risc cpu (cpu name: nx-u8/100) ? instruction system:16-bit instructions ? instruction set:transfer, arithmetic operations, comp arison, logic operations, multiplication/division, bit manipulations, bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic shift, and so on ? on-chip debug function ? minimum instruction execution time approx 30.5 s (at 32.768khz system clock) approx 0.122 s (at 8.192mhz system clock) v dd = 2.2 to 5.5v ? internal memory ? internal 128-kbyte flash rom(64k 16-bit) (including unusable 1kbyte test area) ? internal 2-kbyte data flash (1-kbyte 2) ? internal 4-kbyte ram (4096 8 -bit) ? interrupt controller ? 1 non-maskable interrupt sources (int ernal source: 1, external source: 1) ? 26 maskable interrupt sources (internal source: 22, external source: 4) ? time base counter ? low-speed time base counter 1 channel ? high-speed time base counter 1 channel ? watchdog timer ? generates a non-maskable interrupt upon the first overflow and a system reset occurs upon the second ? free running ? overflow period: 4 types selectable (125ms, 500ms, 2s, and 8s) ? timers ? 8 bits 6ch (16-bit configuration available)
fedl610q174-01 ML610Q174 2/26 ? pwm ? resolution 16 bits 3 channel(igbt control) ? synchronous serial port ? 2ch ? master/slave selectable ? lsb first/msb first selectable ? 8-bit length/16-bit length selectable ? uart ? half-duplex ? txd/rxd 2 channels ? bit length, parity/no parity, odd parity/even parity, 1 stop bit/2 stop bits ? positive logic/negative logic selectable ? built-in baud rate generator ? i 2 c bus interface ? master function only ? fast mode (400kbit/s@8mhz), standard mode (100kbit/s@8mhz) ? successive approximation type a/d converter ? 10-bit a/d converter ? input: 12ch maximum ? conversion time: 12.75 s per channel ? analog comparator ? 2ch ? interrupt allow edge selection and sampling selection ? general-purpose ports 61 maximum ? input-only port 6ch ? output-only port 6ch (including secondary functions) ? input/output 19ch (including secondary functions) ? input/output 30ch (including lcd driver functions) ? lcd driver ? 128 dots max. (32 seg 4 com), 1/1 to 1/4 duty ? frame frequency selectable (approx. 64hz, 73hz, 85hz, 102hz, 32hz, 128hz, 171hz, and 256hz) ? lcd drive stop mode, lcd display mode, all lcds on mode, and all lcds off mode selectable ? lcd drive voltage generation external or internal selectable ? power supply voltage detect function ? judgment voltages: one of 4 levels ? judgment accuracy: 2% (typ.)
fedl610q174-01 ML610Q174 3/26 ? reset ? reset through the reset_n pin ? reset by the watchdog timer (wdt) overflow ? clock ? low-speed clock (this lsi can not guarantee the operation withoug low-speed clock) crystal oscillation (32.768 khz) or built-in rc oscillation (32.7khz) ? high-speed clock built-in oscillation (8.192mhz/8mhz), crystal/c eramic oscillation (8mhz), external clock ? power management ? halt mode: instruction execution by cpu is suspende d (peripheral circuits are in operating states). ? stop mode: stop of low-speed oscillation and high-s peed oscillation (operations of cpu and peripheral circuits are stopped.) ? clock gear: the frequency of high-speed system clock can be changed by software (1/1, 1/2, 1/4, or 1/8 of the oscillation clock) ? block control function: operation of an intact functional block circuit is powerd down. (register reset and clock stop) ? shipment ? 80-pin qfp (qfp80-p-1420-0.80) ? ML610Q174-xxxga (blank product: ML610Q174-nnnga) xxx: rom code number ? guaranteed operating range ? operating temperature: ? 40 c to 85 c ? operating voltage: v dd = 2.2v to 5.5v, v ref = 4.5v to 5.5v
fedl610q174-01 ML610Q174 4/26 block diagram figure 1-1 is a block diagram of the ML610Q174. symbols with an asterisk ?*? indicate that each of them is the secondary or ter tiary function of the corresponding port. program memory flash 128kbyte ram 4096byte interrupt controller cpu (nx-u8/100) large model timing controller ea sp instruction decoder bus controller instruction register tbc int 4 int 6 8bit timer 6 gpio p20 to p23 int 4 p52 to p53 data-bus test0 reset_n osc power v ddl reset & test alu epsw1 3 psw elr1 3 lr ecsr1 3 dsr/csr pc greg 0 15 v dd v ss outclk* uart rxd0* 1 , rxd1* 1 txd0* 1 , txd1* 1 int 2 lsclk* p4 0 t o p4 3 on-chip ice p00 to p03 ssio sck0* 1 , sck1* 1 sin0* 1 , sin1* 1 sout0* 1 , sout1* 1 int 2 wdt int 10bit-adc ain0 to ain11 *3 v ref v dd v ss osc0* 1 int i 2 c int 1 sda* 1 scl* 1 pwm int 3 pwm4* 1 pwm5* 1 lcd driver com0 to com3 *2 seg0 to seg7 lcd bias v l1 , v l2 , v l3 xt0 xt1 p90 to p91 bld pw45ev0* 1 p30 to p35 *3 int 1 p10 to p11 osc1* test1_n p44 t o p47 *3 seg8 to seg23 *2 seg32 to seg39 *2 pw45ev1* 1 pc0 to pc7 * 2 pd0 to pd7 * 2 pf0 to pf7 * 2 p50 to p51 *3 cmp cmp0p 4 cmp0m 4 cmp1p 4 cmp1m 4 2 int pw6ev0* 1 pw6ev1* 1 pwm6* 1 p80 to p85 *2 p36 *1 secondary or tertiary function *2 select i/o port or lcd driver *3 select i/o port or a/d converter input *4 select i/o port or analog comparator input
fedl610q174-01 ML610Q174 5/26 pin configuration ML610Q174 qfp package product seg5 pc3/seg11 pc2/seg10 pc1/seg9 pc0/seg8 seg7 seg6 seg4 seg3 seg2 seg1 seg0 pd3/seg19 pd2/seg18 pd1/seg17 pd0/seg16 p90/led4 1pin 80pin 24pin 25pin 40pin 41pin 65pin 64pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 pc7/seg15 pc6/seg14 pc5/seg13 pc4/seg12 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 p83/com3 vl3 p85/vl2 p84/vl1 p36/lsclk xt1 xt0 v ddl v dd v ss p11/osc1 p10/osc0 reset_n p81/com1 p82/com2 p80/com0 pd7/seg23 pd6/seg22 pd5/seg21 pd4/seg20 pf3/seg35/txd0/pwm4/txd1 pf4/seg36/sin1/pwm4 pf5/seg37/sck1/pwm5 test0 p00/exi0/pw45ev0 p01/exi1/pw6ev0 p02/exi2/rxd0 p03/exi3/rxd1 p20/led0/lsclk/pwm4 test1_n pf1/seg33/sck0 pf2/seg34/ rxd0/sout0 pf0/seg32/sin0 pf7/seg39/txd1/txd0 pf6/seg38/rxd1/sout1/pwm6 p21/led1/outclk/pwm5 p91/led5 p23/led3/tmbout p40/sda/sin0 p41/scl/sck0 p42/rxd0/sout0 p43/txd0/pwm4/txd1 p53/txd1/pwm6/txd0/cmp1p p52/rxd1/sout1/cmp0p p51/ain9/sck1 p50/ain8/sin1 p47/ain7/pwm5/cmp1m p46/ain6/sout0/cmp0m p45/ain5/sck0 p44/ain4/sin0 p33/ain3 p32/ain2 p31/ain1/pw6ev1 p30/ain0/pw45ev1 v ref p34/ain11/pwm4 p35/ain10/pwm5 v ss p22/led2/tm9out
fedl610q174-01 ML610Q174 6/26 list of pins primary function secondary function tertiary function pin no. pin name i/o description pin name i/o description pin name i/o description 1,27 vss ? negative power supply pin ? ? ? ? ? ? 28 v dd ? positive power supply pin ? ? ? ? ? ? 29 v ddl ? power supply for internal logic (internally generated) ? ? ? ? ? ? 34 v l3 ? power supply pin for lcd bias ? ? ? ? ? ? 73 test0 i/o input/output pin for testing ? ? ? ? ? ? 74 test1_n i/o input/output pin for testing ? ? ? ? ? ? 32 reset_n i reset input pin ? ? ? ? ? ? 30 xt0 i low-speed clock oscillation pin ? ? ? ? ? ? 31 xt1 o low-speed clock oscillation pin ? ? ? ? ? ? 24 v ref i reference power supply pin of successive-approximation type adc ? ? ? ? ? ? 75 p00/exi0/ pw45ev0 i input port / external interrupt / pw45ev0 input ? ? ? ? ? ? 76 p01/exi1/ pw6ev0 i input port / external interrupt/ pw6ev0 input ? ? ? ? ? ? 77 p02/exi2/ rxd0 i input port / external interrupt uart0 data input ? ? ? ? ? ? 78 p03/exi3/ rxd1 i input port / external interrupt / uart1 data input ? ? ? ? ? ? 25 p10 i input port osc0 i high-speed clock oscillation pin ? ? ? 26 p11 i input port osc1 o high-speed clock oscillation pin ? ? ? 79 p20/ led0 o output port / led drive lsclk o low-speed clock output pwm4 o pwm4 output 80 p21/ led1 o output port / led drive outclk o low-speed clock output pwm5 o pwm5 output 2 p22/ led2 o output port / led drive ? ? ? tm9out o timer9 output 3 p23/ led3 o output port / led drive ? ? ? tmbout o timerb output 23 p30/ pw45ev1 /ain0 i/o input/output port / pw45ev1 input / successive approximation type adc input ? ? ? ? ? ? 22 p31/ pw6ev1 ain1 i/o input/output port / pw6ev1 input / successive approximation type adc input ? ? ? ? ? ? 21 p32/ ain2 i/o input/output port / successive approximation type adc input ? ? ? ? ? ? 20 p33/ ain3 i/o input/output port / successive approximation type adc input ? ? ? ? ? ? 10 p34/ ain11 i/o input/output port / successive approximation type adc input ? ? ? pwm4 o pwm4 output 11 p35/ ain10 i/o input/output port / successive approximation type adc input ? ? ? pwm5 o pwm5 output 33 p36 i/o input/output port lsclk o low-speed clock output ? ? ?
fedl610q174-01 ML610Q174 7/26 primary function secondary function tertiary function fourthly function pin no. pin name i/o description pin name i/o description pin name i/o description pin name i/o description 6 p40 i/o input/output port sda i/o i 2 c data input/output sin0 i ssio0 data input ? ? ? 7 p41 i/o input/output port scl i/o i 2 c clock input/output sck0 i/o ssio0 synchronou s clock input/output ? ? ? 8 p42 i/o input/output port rxd0 i uart0 data input sout0 o ssio0 data output ? ? ? 9 p43 i/o input/output port txd0 o uart0 data output pwm4 o pwm4 output txd1 o uar1 data output 19 p44/ t0p4ck/ ain4 i/o input/output port / timer0 / pwm4 external clock input/ successive approximation type adc input ? ? ? sin0 i ssio0 data input ? ? ? 18 p45/ t1p5ck/ ain5 i/o input/output port/ timer1 / pwm5 external clock input/ successive approximation type adc input ? ? ? sck0 i/o ssio0 synchronou s clock input/output ? ? ? 17 p46/ t8ap6ck / ain6/ cmp0m i input/output port / timer8,a / pwm6 external clock input / successive approximation type adc input / comparator0 inverting input ? ? ? sout0 o ssio0 data output ? ? ? 16 p47/ t9bck/ ain7/ cmp1m i input/output port / timer9,b external clock input / successive approximation type adc input / comparator1 inverting input ? ? ? pwm5 o pwm5 output ? ? ? 15 p50/ ain8 i/o input/output port / successive approximation type adc input ? ? ? sin1 i ssio1 data input ? ? ? 14 p51/ ain9 i/o input/output port / successive approximation type adc input ? ? ? sck1 i/o ssio1 synchronou s clock input/output ? ? ? 13 p52/ cmp0p i/o input/output port / comparator0 non-inverting input rxd1 i uart1 data input sout1 o ssio1 data output ? ? ? 12 p53/ cmp1p i/o input/output port / comparator1 non-inverting input txd1 o uart1 data input pwm6 o pwm6 output txd0 o uar0 data output 40 p80/ com0 i/o input/output port / lcd common pin ? ? ? ? ? ? ? ? ? 39 p81/ com1 i/o input/output port / lcd common pin ? ? ? ? ? ? ? ? ? 38 p82/ com2 i/o input/output port / lcd common pin ? ? ? ? ? ? ? ? ? 37 p83/ com3 i/o input/output port / lcd common pin ? ? ? ? ? ? ? ? ? 36 p84/ v l1 i/o input/output port / power supply pin for lcd bias ? ? ? ? ? ? ? ? ?
fedl610q174-01 ML610Q174 8/26 primary function secondary function tertiary function fourthly function pin no. pin name i/o description pin name i/o description pin name i/o description pin name i/o description 35 p85/ v l2 i/o input/output port/ power supply pin for lcd bias ? ? ? ? ? ? ? ? ? 4 p90/ led4 o output port / led drive ? ? ? ? ? ? ? ? ? 5 p91/ led5 o output port / led drive ? ? ? ? ? ? ? ? ? 41 seg0 o lcd segment pin ? ? ? ? ? ? ? ? ? 42 seg1 o lcd segment pin ? ? ? ? ? ? ? ? ? 43 seg2 o lcd segment pin ? ? ? ? ? ? ? ? ? 44 seg3 o lcd segment pin ? ? ? ? ? ? ? ? ? 45 seg4 o lcd segment pin ? ? ? ? ? ? ? ? ? 46 seg5 o lcd segment pin ? ? ? ? ? ? ? ? ? 47 seg6 o lcd segment pin ? ? ? ? ? ? ? ? ? 48 seg7 o lcd segment pin ? ? ? ? ? ? ? ? ? 49 pc0 / seg8 i/o input/output port / lcd segment pin ? ? ? ? ? ? ? ? ? 50 pc1 / seg9 i/o input/output port / lcd segment pin ? ? ? ? ? ? ? ? ? 51 pc2 / seg10 i/o input/output port / lcd segment pin ? ? ? ? ? ? ? ? ? 52 pc3 / seg11 i/o input/output port / lcd segment pin ? ? ? ? ? ? ? ? ? 53 pc4 / seg12 i/o input/output port / lcd segment pin ? ? ? ? ? ? ? ? ? 54 pc5 / seg13 i/o input/output port / lcd segment pin ? ? ? ? ? ? ? ? ? 55 pc6 / seg14 i/o input/output port / lcd segment pin ? ? ? ? ? ? ? ? ? 56 pc7 / seg15 i/o input/output port / lcd segment pin ? ? ? ? ? ? ? ? ? 57 pd0 / seg16 i/o input/output port / lcd segment pin ? ? ? ? ? ? ? ? ? 58 pd1 / seg17 i/o input/output port / lcd segment pin ? ? ? ? ? ? ? ? ? 59 pd2 / seg18 i/o input/output port / lcd segment pin ? ? ? ? ? ? ? ? ? 60 pd3 / seg19 i/o input/output port / lcd segment pin ? ? ? ? ? ? ? ? ? 61 pd4 / seg20 i/o input/output port / lcd segment pin ? ? ? ? ? ? ? ? ? 62 pd5 / seg21 i/o input/output port / lcd segment pin ? ? ? ? ? ? ? ? ? 63 pd6 / seg22 i/o input/output port / lcd segment pin ? ? ? ? ? ? ? ? ? 64 pd7 / seg23 i/o input/output port / lcd segment pin ? ? ? ? ? ? ? ? ? 65 pf0 / seg32 i/o input/output port / lcd segment pin ? ? ? sin0 i ssio0 data input ? ? ? 66 pf1 / seg33 i/o input/output port / lcd segment pin ? ? ? sck0 i/o ssio0 synchronou s clock input/output ? ? ? 67 pf2 / seg34 i/o input/output port / lcd segment pin rxd0 i uart0 data input sout0 o ssio0 data output ? ? ? 68 pf3 / seg35 i/o input/output port / lcd segment pin txd0 o uart0 data output pwm4 o pwm4 output txd1 o uar1 data output 69 pf4 / seg36 i/o input/output port / lcd segment pin ? ? ? sin1 i ssio1 data input pwm4 o pwm4 output 70 pf5 / seg37 i/o input/output port / lcd segment pin ? ? ? sck1 i/o ssio1 synchronou s clock input/output pwm5 o pwm5 output 71 pf6 / seg38 i/o input/output port / lcd segment pin rxd1 i uart1 data input sout1 o ssio1 data output pwm6 o pwm6 output 72 pf7 / seg39 i/o input/output port / lcd segment pin txd1 o uart1 data input ? ? ? txd0 o uar0 data output
fedl610q174-01 ML610Q174 9/26 pin description pin name i/o description primary/ secondary logic power supply v ss ? negative power supply pin ? ? v dd ? positive power supply pin ? ? v ddl ? positive power supply pin for internal logic (internally generated). connect capacitors (c l ) (see measuring circuit 1) between this pin and v ss . ? ? v l1 ? power supply pins for lcd bias (externa l input). this function is allocated to the primary functi on of the p84 pin. ? ? v l2 ? power supply pins for lcd bias (externa l input). this function is allocated to the primary functi on of the p85 pin. ? ? v l3 ? power supply pins for lcd bias (external input) ? ? test test0 i/o input/output pin for testing. this pi n has a pull-down resistor built in. ? positive test1_n i/o input/output pin for testing. this pi n has a pull-up resistor built in. ? negative system reset_n i reset input pin. when this pin is set to a ? l ? level, the device is placed in system reset mode and the internal circuit is initialized. if after that this pin is set to a ? h ? level, program execution starts. this pin has a pull-up resistor built in. ? negative xt0 i ? ? xt1 o crystal connection pin for low-speed clock. a 32.768 khz crystal oscillator (see measuring circuit 1) is connected to this pin. capacitors c dl and c gl are connected across this pin and v ss as required. ? ? osc0 i ? ? osc1 o crystal/ceramic connection pin for high-speed clock. a 8mhz crystal or ceramic is connected to this pin. capacitors c dh and c gh (see measuring circuit 1) are connected across this pin and v ss . ? ? lsclk o low-speed clock output. this function is allocated to the secondary function of the p20/p36 pin. secondary ? outclk o high-speed clock output. this functi on is allocated to the secondary function of the p21 pin. secondary ? general-purpose input port p00 to p03 i p10 to p11 i general-purpose input ports. provided with a secondary function for each port. cannot be used as ports if their secondary functions are used. primary positive general-output input port p20 to p23 o general-purpose output ports.provided with a secondary function for each port. cannot be used as ports if their secondary functions are used. primary positive p90 to p91 o general-purpose output ports.provided with a secondary function for each port. cannot be used as ports if their secondary functions are used. primary positive general-purpose input/output port p30 to p36 p40 to p47 p50 to p53 p80 to p85 general-purpose input/output ports.pro vided with a secondary function for each port. cannot be used as ports if their secondary functions are used. pc0 to pc7 pd0 to pd7 pf0 to pf7 i/o general-purpose input/output ports.pro vided with a lcd segment for each port. cannot be used as ports if lcd segment are used. primary positive
fedl610q174-01 ML610Q174 10/26 pin name i/o description primary/ secondary logic uart txd0 o uart0 data output pin. allocated to t he secondary function of the p43 and pf3 pins and the fourthly function of the p53 and pf7 pins. secondary fourthly positive rxd0 i uart0 data input pin. allocated to t he primary function of the p02 pin and the secondary function of the p42 and pf2 pins. secondary positive txd1 o uart1 data output pin. allocated to t he secondary function of the p53 and pf7 pins and the fourthly function of the p43 and pf3 pins. secondary fourthly positive rxd1 i uart1 data input pin. allocated to t he primary function of the p03 pin and the secondary function of the p52 and pf6 pins. secondary positive i 2 c bus interface sda i/o i 2 c data input/output pin. this pin is us ed as the secondary function of the p40 pin. this pin has an nmos open drain output. when using this pin as a function of the i 2 c, externally connect a pull-up resistor. secondary positive scl i/o i 2 c clock output pin. this pin is used as the secondary function of the p41 pin. this pin has an nmos open drain output. when using this pin as a function of the i 2 c, externally connect a pull-up resistor. secondary positive synchronous serial (ssio) sin0 i synchronous serial data input pin. allo cated to the tertiary function of the p40 and p44 and pf0 pins. tertiary positive sck0 i/o synchronous serial clock input/output pi n. allocated to the tertiary function of the p41 and p45 and pf1 pins. tertiary ? sout0 o synchronous serial data output pin. allo cated to the tertiary function of the p42 and p46 and pf2 pins. tertiary positive sin1 i synchronous serial data input pin. allo cated to the tertiary function of the p50 and pf4 pins. tertiary positive sck1 i/o synchronous serial clock input/output pi n. allocated to the tertiary function of the p51 and pf5 pins. tertiary ? sout1 o synchronous serial data output pin. allo cated to the tertiary function of the p52 and pf6 pins. tertiary positive pwm pwm4 o pwm4 output pin. allocated to the tert iary function of the p34 and p43 and p20 and pf3 and pf4 pins. tertiary positive pwm5 o pwm5 output pin. allocated to the tert iary function of the p35 and p47 and p21 and pf5 pins. tertiary positive pwm6 o pwm6 output pin. allocated to the tert iary function of the p53 and pf6 pins. tertiary positive t0p4ck i external clock input pin for timer 0 and pwm4. allocated to the primary function of the p44 pin. primary ? t1p5ck i external clock input pin for timer 1 and pwm5. allocated to the primary function of the p45 pin. primary ? t8ap6ck i external clock input pin for timer 8 and timer a and pwm6. allocated to the primary function of the p46 pin. primary ? pw45ev0 pw45ev1 i control start /stop pin for pwm4 and pwm5. allocated to the primary function of the p00 and p30 pins. primary ? pw6ev0 pw6ev1 i control start /stop pin for pwm6. alloca ted to the primary function of the p01 and p31 pins. primary ? external interrupt exi0?exi3 i external maskable interrupt input pins. it is possible, for each bit, to specify whether the interrupt is enabled and select the interrupt edge by software. allocated to the primary f unction of the p00?p03 pins. primary positive/ negative
fedl610q174-01 ML610Q174 11/26 pin name i/o description primary/ secondary logic timer t0p4ck i external clock input pin for timer 0 and pwm4. allocated to the primary function of the p44 pin. primary ? t1p5ck i external clock input pin for timer 1 and pwm5. allocated to the primary function of the p45 pin. primary ? t8ap6ck i external clock input pin for timer 8 and timer a and pwm6. allocated to the primary function of the p46 pin. primary ? t9bck i external clock input pin for timer 9 and timer b. allocated to the primary function of the p47 pin. primary ? tm9out o timer9 overflow output pin. allocate d to the secondary function of the p22 pin. tertiary positive tmbout o timerb overflow output pin. allocate d to the secondary function of the p23 pin. tertiary positive led drive led0-led5 o pins for led driving. allocated to t he primary function of the p20?p23 pins and p90?p91 pins. primary positive/ negative successive-approximation type a/d converter v ref i reference power supply pin for successive approximation type a/d converter. ? ? ain0?ain11 i analog inputs to ch0?ch11 of the successive-approximation type a/d converter. allocated to the secondary fu nction of the p30 to p35 and p44 to p47 and p50 to p51 pins. ? ? analog comparator cmp0p i non-inverting input for comparator0. this pin is used as the primary function of the p52 pin. ? ? cmp0m i inverting input for comparator0. this pin is used as the primary function of the p46 pin. ? ? cmp1p i non-inverting input for comparator1. this pin is used as the primary function of the p53 pin. ? ? cmp1m i inverting input for comparator1. this pin is used as the primary function of the p47 pin. ? ? lcd driver com0 to com3 o lcd common output pins. ? ? seg0 to seg7 o lcd segment output pins. ? ? seg8 to seg23 seg32 to seg39 o lcd segment output pins. allocated to the secondary function of the pc0 to pc7 and pd0 to pd7 and pf0 to pf7 pins. ? ?
fedl610q174-01 ML610Q174 12/26 termination of unused pins how to terminate unused pins pin recommended pin termination reset_n open test0 open test1_n open v ref connect to v dd v l1 open p00 to p03 connect v dd or v ss p10 to p11 connect v dd or v ss p20 to p23 open p30 to p33 ain0 to ain3 open p34 to p35 ain11, ain10 open p36 open p40 to p43 open p44 to p47 ain4 to ain7 open p50 to p51 ain8 to ain9 open p52 to p53 open p80 to p85 open p90 to p91 open seg0 to seg7 open pc0 to pc7 seg8 to15 open pd0 to pd7 seg16 to 23 open pf0 to pf7 seg32 to 39 open note: for unused input ports or unused input/output ports, if the corresponding pins are configured as high-impedance inputs and left open, the supply current may become excessively large. therefore, it is recommended to configure those pins as either inputs with a pull-down resi stor/pull-up resistor or outputs.
fedl610q174-01 ML610Q174 13/26 electrical characteristics absolute maximum ratings (v ss = 0v) parameter symbol condition rating unit power supply voltage 1 v dd ta = 25 c ? 0.3 to +7.0 v power supply voltage 2 v ddl ta = 25 c ? 0.3 to +3.6 v power supply voltage 3 v l1 ta = 25 c ? 0.3 to +2.33 v power supply voltage 4 v l2 ta = 25 c ? 0.3 to +4.66 v power supply voltage 5 v l3 ta = 25 c ? 0.3 to +7.0 v reference voltage v ref ta = 25 c ? 0.3 to v dd +0.3 v analog input voltage v ai ta = 25 c ? 0.3 to v dd +0.3 v input voltage v in ta = 25 c ? 0.3 to v dd +0.3 v output voltage v out ta = 25 c ? 0.3 to v dd +0.3 v output current 1 i out1 port3,4,5,8,c,d,f ta = 25 c ? 12 to +11 ma output current 2 i out2 port2,9 ta = 25 c ? 12 to +20 ma power dissipation pd ta = 25 c 1 w storage temperature t stg D ? 55 to +150 c recommended operating conditions (v ss = 0v) parameter symbol condition range unit operating temperature t op D ? 40 to +85 c operating voltage v dd D 2.2 to 5.5 v reference voltage v ref D 4.5 to v dd v analog input voltage v ai D v ss to v ref v operating frequency (cpu) f op D 30k to 8.4m hz low-speed crystal oscillation frequency f xtl D 32.768k hz capacitor externally connected to v dd pin c v D 10 30% f capacitor externally connected to v ref pin c av D 1 30% f c dl 12 to 25 low-speed crystal oscillation external capacitor c gl use 32.768khz crystal oscillator dt-26 (daishinku corp.) 12 to 25 pf high-speed crystal/ceramic oscillation frequency f xth D 8m / 8.192m hz c dh D 47 30% high-speed crystal oscillation external capacitor* c gh D 47 30% pf capacitor externally connected to v ddl pin c l D 10 30% f * c gh and c dh are built into, external capacity is unnecessary for cstls8m00g56 (made by murata mfg.).
fedl610q174-01 ML610Q174 14/26 flash memory operating conditions (v ss = 0v) parameter symbol condition range unit data flash memory, at write/erase -40 to +85 operating temperature t op flash rom, at write/erase 0 to +40 c operating voltage v dd at write/erase 2.2 to 5.5 v c epd data flash memory 6000 maximum rewrite count c epp flash rom 100 times data retention period y dr D 10 years parameter symbol condition min. typ. max. unit block erase time t berase D D D 100 sector erase time t serase D D D 100 ms 1 word write time t write D D D 40 s * 1 : at the writing of a flas h rom, it is necessary to supply voltage to v ddl pin within the limits of the above-mentioned regulation. pulldown resistance is built in the v pp pin. dc characteristics (1 of 7) (v dd =2.2 to 5.5v, v ss =0v, ta= ? 40 to +85 c, unless otherwise specified) parameter symbol conditio n min. typ. max. unit measuring circuit high-speed crystal oscillation start time t xth D D 2 20 ms low-speed crystal oscillation start time* 1 t xtl D D 0.6 2 s low-speed rc oscillator frequency f lcr ta= -10 to 60 c typ -5% 32.7k typ +5% hz pll oscillation frequency f pll lsclk=32.768khz 1000 clock average typ -1% 8.192 typ +1% mhz reset pulse width p rst D 100 D D reset noise rejection pulse width p nrst D D D 0.4 s 1 * 1 : use 32.768khz crystal oscillator dt-26 (daishinku) with capacitance c gl /c dl 12pf. reset reset_n reset by reset_n pin p rst vil1 vil1
fedl610q174-01 ML610Q174 15/26 dc characteristics (2 of 7) (v dd =2.2 to 5.5v, v ss =0v, ta= ? 40 to +85 c, unless otherwise specified) parameter symbol conditio n min. typ. max. unit meas uring circuit ld3 to 0 = 0h 2.35 ld3 to 0 = 3h 2.80 ld3 to 0 = 9h 3.70 bld threshold voltage v bld ta = 25 c ld3 to 0 = fh typ. -2% 4.60 typ. +2% v 1 dc characteristics (3 of 7) (v dd =2.2 to 5.5v, v ss =0v, ta= ? 40 to +85 c, unless otherwise specified) parameter symbol conditio n min. typ. max. unit meas uring circuit cmpnm v in D 0 D v dd -1.4 common mode input voltage cmpnp v in D 0 D v dd v input offset voltage v cmpof D D 5 100 mv response time t cmp cmpnp = cmpnm 100mv D D 1 s supply current operating i cmp cmp0,cmp1 operating D 30 D a 1 dc characteristics (4 of 7) (v dd =2.2 to 5.5v, v ss =0v, ta= ? 40 to +85 c, unless otherwise specified) parameter symbol conditio n min. typ. max. unit meas uring circuit r lh ta = -10 to +70 typ. -5% 200 typ. +5% lcd built-in division resistance r ll ta = -10 to +70 typ. -20% 20 typ. +20% k 1 dc characteristics (5 of 7) (v dd =2.2 to 5.5v, v ss =0v, ta= ? 40 to +85 c, unless otherwise specified) parameter symbol condit ion min. typ. max. unit meas uring circuit -40 to +35 D 0.7 6 supply current 1 idd1 cpu: in stop state low-speed/high-speed oscillation: stopped v dd =3.0v -40 to +85 D 0.7 22 -40 to +35 D 2.0 7 supply current 2 idd2 cpu: in halt state (ltbc,wbc: operating *2 ) high-speed oscillation: stopped v dd =3.0v -40 to +85 D 2.0 24 -40 to +35 D 13 20 supply current 3 idd3 cpu: running at 32khz* 1 high-speed oscillation: stopped v dd =3.0v -40 to +85 D 13 42 a supply current 4 idd4 cpu: running at 8mhz crystal/ceramic oscillating mode* 2 v dd =5.0v D 5 8 ma 1 * 1 : case when the cpu operating rate is 100% (with no halt state) * 2 : significant bits of blkcon0 to blkcon7 registers are all ?1?.
fedl610q174-01 ML610Q174 16/26 dc characteristics (6 of 7) (v dd =2.2 to 5.5v, v ss =0v, ta= ? 40 to +85 c, unless otherwise specified) parameter symbol conditio n min. typ. max. unit measuring circuit voh1 ioh1 = ? 0.5ma v dd ? 0.5 D D output voltage 1 (p20 to p23) (p30 to p36) (p40 to p47) (p50 to p53) (p80 to p85) (p90 to p91) (pc0 to pc7) (pd0 to pd7) (pf0 to pf7) vol1 iol1 = +0.5ma D D 0.5 output voltage 2 (p20?p23) (p90-p91) vol2 when led drive mode is selected iol2 = +10ma v dd 4.5v D D 0.5 output voltage 3 (p40?p41) vol3 when i 2 c mode is selected iol3 = +3ma D D 0.4 v 2 iooh voh = v dd (in high-impedance state) D D 1 output leakage current (p20 to p23) (p30 to p36) (p40 to p47) (p50 to p53) (p80 to p85) (p90 to p91) (pc0 to pc7) (pd0 to pd7) (pf0 to pf7) iool vol = v ss (in high-impedance state) ? 1 D D a 3 vl3=3v vol=0.3v 15 40 D iol1 vl3=5v vol=0.5v 100 200 D vl3=3v voh=2.7v D -30 -15 output current 1 com0 to com3 ioh1 vl3=5v voh=4.5v D -90 -45 vl3=3v vol=0.3v 15 30 D iol2 vl3=5v vol=0.5v 70 150 D vl3=3v voh=2.7v D -13 -6 output current 2 seg0 to seg23 seg32 to seg39 ioh2 vl3=5v voh=4.5v D -40 -20 a 3 iih1 vih1 = v dd 0 D 1 input current 1 (reset_n) (test1_n) iil1 vil1 = v ss ? 1500 ? 300 ? 20 iih2 vih2 = v dd (when pulled down) 2 30 250 iil2 vil2 = v ss (when pulled up) ? 250 ? 30 ? 2 iih2z vih2 = v dd (in high-impedance state) D D 1 input current 2 (p00 to p03) (p10 to p11) (p30 to p36) (p40 to p47) (p50 to p53) (p80 to p85) (pc0 to pc7) (pd0 to pd7) (pf0 to pf7) iil2z vil2 = v ss (in high-impedance state) -1 D D iih3 vih3 = v dd 20 300 1500 input current 3 (test0) iil3 vil3 = v ss -1 D D a 4
fedl610q174-01 ML610Q174 17/26 dc characteristics (7 of 7) (v dd =2.2 to 5.5v, v ss =0v, ta= ? 40 to +85 c, unless otherwise specified) parameter symbol conditio n min. typ. max. unit measuring circuit vih1 D 0.7 v dd D v dd input voltage 1 (reset_n) (test0) (test1_n) (p00 to p03) (p10 to p11) (p30 to p36) (p40 to p47) (p50 to p53) (p80 to p85) (pc0 to pc7) (pd0 to pd7) (pf0 to pf7) vil1 D 0 D 0.3 v dd v 5 input pin capacitance (reset_n) (test0) (test1_n) (p00 to p03) (p10 to p11) (p30 to p36) (p40 to p47) (p50 to p53) (p80 to p85) (pc0 to pc7) (pd0 to pd7) (pf0 to pf7) cin f = 10khz v rms = 50mv ta = 25 c D D 10 pf D
fedl610q174-01 ML610Q174 18/26 measuring circuits measuring circuit 1 measuring circuit 2 input pins v vih vil output pins ( *2 ) ( *1 ) v dd v ref v ddl v ss v l1 v l2 v l3 (*1) input logic circuit to determi ne the specified measuring conditions. (*2) measured at the specified output pins. a v dd v ref v ddl c l c v v l1 v l3 c l3 c l2 c l1 32.768khz crystal c gl c dl xt0 xt1 8mhz crystal c gh c dh osc0 osc1 v ss v l2 c v 10 f c l 10 f c gl 12pf c dl 12pf c gh 47pf c dh 47pf c l1 ,c l2 ,c l3 0.22 f 32.768khz crystal oscillator (dmx-26 daishinku corp.) 8mhz crystal oscillator cstls8m00g56 murata corp. it has built-in c gh , and c dh
fedl610q174-01 ML610Q174 19/26 measuring circuit 3 measuring circuit 4 measuring circuit 5 vih vil *1: input logic circuit to determine the specified measuring conditions. v dd v ref v ddl v ss waveform monitoring output pins input pins (*1) a *3: measured at the specified input pins. (*3) v dd v ref v ddl v ss output pins input pins input pins a vih vil (*1) input logic circuit to determi ne the specified measuring conditions. (*2) measured at the specified output pins. ( *2 ) (*1) v dd v ref v ddl v ss output pins
fedl610q174-01 ML610Q174 20/26 ac characteristics (external interrupt) (v dd =2.2 to 5.5v, v ss =0v, ta= ? 40 to +85 c, unless otherwise specified) parameter symbol conditio n min. typ. max. unit external interrupt disable period t nul interrupt: enabled (mie = 1), cpu: nop operation 2.5 sysclk D 3.5 sysclk s t nul p00?p03 (rising-edge interrupt) p00?p03 (falling-edge interrupt) p00?p03 (both-edge interrupt) t nul t nul
fedl610q174-01 ML610Q174 21/26 ac characteristics (synchronous serial port) (v dd =2.2 to 5.5v, v ss =0v, ta= ? 40 to +85 c, unless otherwise specified) parameter symbol conditio n min. typ. max. unit high-speed oscillation stopped 10 D D s sck input cycle (slave mode) t scyc during high-speed oscillation 500 D D ns sck output cycle (master mode) t scyc D D sck (*1) D sec high-speed oscillation stopped 4 D D s sck input pulse width (slave mode) t sw during high-speed oscillation 200 D D ns sck output pulse width (master mode) t sw D sck (*1) 0.4 sck (*1) 0.5 sck (*1) 0.6 sec sout output delay time (slave mode) t sd D D D 180 ns sout output delay time (master mode) t sd D D D 80 ns sin input setup time (slave mode) t ss D 50 D D ns sin input hold time t sh D 50 D D ns *1: clock period selected by snck3?0 of the serial port n mode register (sionmod1) t sd sckn* sinn* soutn *: indicates the secondary function of the corresponding port. t sd t ss t sh t sw t sw t scyc
fedl610q174-01 ML610Q174 22/26 ac characteristics (i 2 c bus interface: standard mode 100khz) (v dd =2.2 to 5.5v, v ss =0v, ta= ? 40 to +85 c, unless otherwise specified) rating parameter symbol condition min. typ. max. unit scl clock frequency f scl ? 0 ? 100 khz scl hold time (start/restart condition) t hd:sta ? 4.0 ? ? s scl ?l? level time t low ? 4.7 ? ? s scl ?h? level time t high ? 4.0 ? ? s scl setup time (restart condition) t su:sta ? 4.7 ? ? s sda hold time t hd:dat ? 0 ? ? s sda setup time t su:dat ? 0.25 ? ? s sda setup time (stop condition) t su:sto ? 4.0 ? ? s bus-free time t buf ? 4.7 ? ? s ac characteristics (i2c bus interface: fast mode 400khz) (v dd =2.2 to 5.5v, v ss =0v, ta= ? 40 to +85 c, unless otherwise specified) rating parameter symbol condition min. typ. max. unit scl clock frequency f scl ? 0 ? 400 khz scl hold time (start/restart condition) t hd:sta ? 0.6 ? ? s scl ?l? level time t low ? 1.3 ? ? s scl ?h? level time t high ? 0.6 ? ? s scl setup time (restart condition) t su:sta ? 0.6 ? ? s sda hold time t hd:dat ? 0 ? ? s sda setup time t su:dat ? 0.1 ? ? s sda setup time (stop condition) t su:sto ? 0.6 ? ? s bus-free time t buf ? 1.3 ? ? s p41/scl p40/sda start condition restart condition stop condition t buf t hd:sta t low t high t su:sta t hd:sta t su:dat t hd:dat t su:sto
fedl610q174-01 ML610Q174 23/26 electrical characteristics of successive approximation type a/d converter (v dd =4.5 to 5.5v, v ss =0v, ta= ? 40 to +85 c, unless otherwise specified) parameter symbol conditio n min. typ. max. unit resolution n D D D 10 bits integral non-linearity error idl 2.7v v ref 5.5v ? 4 D +4 differential non-linearity error dnl 2.7v v ref 5.5v ? 3 D +3 zero-scale error v off D ? 4 D +4 full-scale error fse D ? 4 D +4 lsb input impedance r i D D D 5k reference voltage v ref 4.5 D v dd v conversion time t conv hsclk=3.0m to 8.4mhz D 102 D /ch : period of high-speed clock (hsclk) a v dd v ref v ddl v ss analog input 10 f - r i 5k a in0 a in11 1 f 0.1 f + 10 f reference voltage
fedl610q174-01 ML610Q174 24/26 package dimensions notes for mounting the su rface mount type package the surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact lapis semiconductor?s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
fedl610q174-01 ML610Q174 25/26 revision history page document no. date previous edition current edition description fedl610q174-01 oct 25, 2013 ? ? final edition 1
fedl610q174-01 ML610Q174 26/26 notes no copying or reproduction of this document, in part or in whole, is permitted without the consent of lapis semiconductor co., ltd. the content specified herein is subject to change for improvement without notice. the content specified herein is for the purpose of introducing lapis semiconductor's products (hereinafter "products"). if you wish to use any such product, pleas e be sure to refer to the specifications, which can be obtained from lapis semiconductor upon request. examples of application circuits, circuit constants a nd any other information contained herein illustrate the standard usage and operations of the products. the peri pheral conditions must be taken into account when designing circuits for mass production. great care was taken in ensuring the accuracy of the in formation specified in this document. however, should you incur any damage arising from any inaccuracy or misprint of such information, lapis semiconductor shall bear no responsibility for such damage. the technical information specified herein is intended on ly to show the typical functions of and examples of application circuits for the products. lapis semiconducto r does not grant you, exp licitly or implicitly, any license to use or exercise intellectual property or other rights held by lapis semiconductor and other parties. lapis semiconductor shall bear no responsibility whatso ever for any dispute arising from the use of such technical information. the products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). the products specified in this document are not designed to be radiation tolerant. while lapis semiconductor always makes efforts to enhance the quality and reliability of its products, a product may fail or malfunction for a variety of reasons. please be sure to implement in your equipment usi ng the products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any product, such as derating, redundancy, fire control and fail-safe desi gns. lapis semiconductor shall bear no responsibility whatsoever for your use of any product outside of the prescribed scope or not in accordance with the instruction manual. the products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (suc h as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-controller or other safety device). lapis semiconductor shall bear no responsibility in any way for use of any of the products for the above special purposes. if a product is intended to be used for any such special purpose, please contact a rohm sales representative before purchasing. if you intend to export or ship overseas any product or technology specified herein that may be controlled under the foreign exchange and the foreign trade law, you will be required to obtain a license or permit under the law. copyright 2013 lapis semiconductor co., ltd.

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